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INTEGRATED CIRCUITS
DATA SHEET
TDA4800 Vertical deflection circuit for monitor applications
Product specification Supersedes data of February 1992 File under Integrated Circuits, IC02 1997 Mar 27
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
FEATURES * Fully integrated, few external components * RC oscillator with wide sync range of 1 : 3 (e.g. 50 to 150 Hz) * Synchronization by positive or negative going sync pulse * Blanking pulse duration is determined externally * Dual frequency criterion for automatic amplitude switch-over (e.g. 50 to 60 Hz) * Guard circuit for screen protection * Sawtooth generator with buffer stage supplied by external voltage * Preamplifier * Power output stage with thermal and SOAR protection * Flyback generator * Internal voltage stabilizer. QUICK REFERENCE DATA SYMBOL VP1 VP2 IP I7(p-p) fsync V3 V3 Tamb Notes 1. Measured in Fig.4. 2. fo = 45 Hz (fsync(max) = 3fo). 3. Ptot = 3.6 W for Rth(j-a) = 20 K/W. ORDERING INFORMATION TYPE NUMBER TDA4800 PACKAGE NAME DBS13P DESCRIPTION plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) PARAMETER supply voltage (pin 6) supply voltage (pin 10) supply current (pins 6 and 10) output current (peak-to-peak value) picture frequency positive sync input pulse negative sync input pulse operating ambient temperature note 3 notes 1 and 2 note 1 CONDITIONS 10 10 - - - 1.0 -0.5 -20 MIN. - - 215 - - - - - TYP. GENERAL DESCRIPTION
TDA4800
The TDA4800 is an integrated circuit for vertical deflection primarily in monitors (and TV receivers). The complete circuit consists of 11 main functional blocks as shown in Fig.1.
MAX. 30 45 - 2.6 135 6.0 -0.7 +70 V V
UNIT
mA A Hz V V C
VERSION SOT141-6
1997 Mar 27
2
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
BLOCK DIAGRAM
TDA4800
handbook, full pagewidth
TDA4800
BLANKING PULSE GENERATOR +2 V GUARD CIRCUIT VOLTAGE STABILIZER
SYNC CIRCUIT
OSCILLATOR
RAMP BUFFER GENERATOR STAGE
PREAMPLIFIER
POWER OUTPUT STAGE THERMAL AND SOAR PROTECTION
FLYBACK GENERATOR
FREQUENCY DETECTOR
1
2
3
4 R3
5
6
7
8 C8
9
10
11
12
13
P1 R4 C1 R17 R2 D1 1N4148 linearity vertical deflection unit 6.5 R6 R7 C11 6.5 mH R10 C7 R15 R14 D2 BAX18
C4
frequency criterion
R1 (frequency)
R13 C5 C9 C6
C2
R5
C10
R12
or sync input blank output
P2 amplitude R8 R16 R9 R11 C12
Vamplitude VP2 = 23 V
MHA590
Fig.1 Block diagram.
1997 Mar 27
3
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
PINNING SYMBOL PIN OSCR OSCC SYBO SOUT PREI VP1 OUTP GND CFLY VP2 SGEN BPDU FRQC 1 2 3 4 5 6 7 8 9 10 11 12 13 DESCRIPTION oscillator resistor oscillator capacitor sync input; blanking pulse output sawtooth output preamplifier input supply voltage 1 deflection output ground pin for the flyback generator capacitor supply voltage 2 sawtooth generator blanking pulse duration frequency criterion
CFLY 9 VP2 10 SGEN 11 BPDU 12 FRQC 13
MHA584
TDA4800
handbook, halfpage
OSCR 1 OSCC 2 SYBO 3 SOUT 4 PREI 5 VP1 6 OUTP 7
TDA4800
GND 8
Fig.2 Pin configuration.
1997 Mar 27
4
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
FUNCTIONAL DESCRIPTION The complete circuit consists of the following functional blocks as shown in Fig.1: 1. Oscillator 2. Synchronization circuit 3. Blanking pulse generator 4. Frequency detector and storage 5. Ramp generator 6. Buffer stage 7. Preamplifier 8. Power output stage 9. Flyback generator 10. Guard circuit 11. Voltage stabilizer. Ramp generator (pin 11) Oscillator (pins 1 and 2) The oscillator is an RC-oscillator with a threshold value switch, which ensures very good frequency stability. The upper and lower threshold voltages are defined by an internal voltage divider. An external capacitor C1 at pin 2 is charged by a constant current source. When the scan voltage of C1 reaches the upper threshold voltage, oscillator flyback starts. Capacitor C1 discharges via an internal resistor and transistor until the lower threshold is reached. The constant charge current and free-running frequency fo are adjusted by an external resistor R1 at pin 1: 1 f o = -------------------------------- with K = 0.68. K x R1 x C1 Synchronization circuit (pin 3) A positive- or negative-going pulse fed to pin 3 synchronizes the oscillator by lowering the upper threshold voltage. The synchronizing range is fo to 3fo. For example: fo = 50 Hz fsync(max) = 150 Hz. Blanking pulse generator (pin 3) Also at pin 3 a blanking pulse is available. Diode D1 separates the synchronization pulse from the blanking pulse. During scanning, the external capacitor C6 at pin 12 is charged to an internal stabilized voltage Vstab2. The blanking pulse starts with the beginning of oscillator flyback; then capacitor C6 discharges via the external resistor R13 at pin 12. The blanking pulse stops when the capacitor voltage is 12Vstab2. 1997 Mar 27 5
TDA4800
The blanking pulse duration is determined by the values of external components R13 and C6 at pin 12: tbl = R13 x C6 x Ln2. Frequency detector with storage (pin 13) At the end of the scanning period a frequency detector detects the oscillator frequency (see "Note" below). When this frequency is above the threshold a flip-flop is set to store this information. The output is an open collector output. NOTE Frequency detector change-over at pin 13 from low (= low frequency) to high (= high frequency) is determined by fo: fthreshold = 1.23 x fo.
The ramp generator consists of two external series capacitors C4 and C5, external charge resistor R12 (connected to pin 11), and an internal differential amplifier which is synchronously switched by the oscillator. External capacitors C4 and C5 at pin 11 are charged by the charging current via the external charge resistor R12 until oscillator flyback starts. C4 and C5 are then discharged via pin 11 by an internal resistor and transistor. This generates a positive-going ramp voltage. Buffer stage (pin 4) The buffer stage consists of two emitter followers. The ramp voltage is fed via the buffer stage and is available at pin 4 with a low ohmic output impedance. With R4 and P1 it generates a ramp function, which, together with the feedback network of the deflection yoke, gives a high degree of linearity at the picture tube. The linearity can be adjusted by P1. Preamplifier (pin 5) The preamplifier is a differential amplifier. The non-inverting input is fixed at about 2 V by an internal voltage divider. The inverting input at pin 5 is connected to the ramp voltage via R3 and feedback network P2, R5 to R11, R15, R16, C7, C10 and C11. Power output stage (pin 7) The power output stage is an amplifier with a quasi-complementary class-B output. The output is connected to pin 7. The power stage includes SOAR and thermal protection.
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
Flyback generator (pin 9) The flyback generator has an external capacitor C8 at pin 9. During scanning, the internal circuit switches pin 9 almost to ground; thereby C8 is charged by the supply voltage via external components R14 and D2. During the flyback time pin 9 is switched almost to the supply voltage, so that the supply voltage for the power output stage (pin 6) is nearly doubled. This high flyback voltage ensures a very short flyback time. Guard circuit (pin 3) When the vertical deflection current is absent (e.g. short-circuited, or open-circuited of the yoke) the guard circuit changes the blanking pulse at pin 3 into a DC signal which blanks the beam current to protect the screen. Also an oscillator defect (C1 short-circuited or R1 disconnected from pin 1) switches on the guard circuit. INTERNAL CIRCUITRY Voltage stabilizer
TDA4800
The voltage stabilizer circuit provides a stable operating voltage of about 7.5 V for several internal circuits of the TDA4800.
handbook, full pagewidth
10
11
12
13
Vstab
TDA4800
1
2
3
4
5
6
7
8
9
MHA588
Fig.3 Internal circuitry.
1997 Mar 27
6
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL V2 V11 V12 V13 V10 V9 V7 V6 V5 V4 V3 I1 I3 I4 I6, I7, I8 I9 I11 Tstg Tamb Tj Ptot VESD Notes storage temperature operating ambient temperature junction temperature total power dissipation ESD sensitivity note 2 note 3 note 2 note 4 -1.5 -0.1 -25 -20 - - -2000 currents supply voltages (VP) voltages PARAMETER CONDITIONS 0 0 0 0 0 0 0 0 0 0 -0.7 0 +3 0 MIN. 6 24 6 50 50 50 60 60 6 24 +6 -1 -10 -5 note 1 +1.5 +30 +150 +70 150 -
TDA4800
MAX. V V V V V V V V V V V
UNIT
mA mA mA A mA C C C W V
+2000
1. I6, I7 and I8 are limited by SOAR protection circuit that ensures that short-circuiting between the output pin 7 and supply voltage or ground does not destroy the output stage. A short-circuit may be soldered into the printed-circuit board or may sometimes (non-periodically) occur in the applied circuit. 2. The maximum value for the operating ambient temperature range and the power dissipation depends on the heatsink. 3. Internally limited by thermal protection: switching temperature point at Tj = 150 8 C. 4. Human body model: 1.5 k, 100 pF, 5 pulses. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Rth(j-mb) PARAMETER thermal resistance from junction to ambient thermal resistance from junction to mounting base VALUE 20 5 UNIT K/W K/W
1997 Mar 27
7
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
TDA4800
CHARACTERISTICS All voltages are measured to GND (ground; pin 8); Tamb = 25 C; VP = 23 V; unless otherwise specified. SYMBOL VP1 VP2 I10 I6 I6 V7(min) V7(max) V9 I7 I9 I5 V1 V3 R3 I3 tbl V11 I11 V13 I13 V4 I4 V3 V3 f 1 ---- x ------------f T mb f 1 ---- x ---------f V P fo ----------f sync PARAMETER supply voltage (pin 6) supply voltage (pin 10) supply current supply current supply current minimum output voltage maximum output voltage output voltage during flyback output current output current preamplifier input current stabilized voltage blanking pulse output voltage blanking pulse output resistance blanking pulse output current blanking pulse duration output voltage ramp generator output current ramp generator output voltage frequency detector lower frequency I13 = 1 mA R = 100 k; C = 10 nF (pin 12) V10 = 25 V; V5 = 3 V without load V6 = 25 V; V5 = 1 V without load V6 = 25 V; V5 = 3 V without load I7 = 1 A I7 = -1 A I9 = -1 A CONDITIONS MIN. 10 10 - - - - - - - - 6.1 - - 0 640 0.3 -2 - - 0 - positive sync negative sync without sync 1.0 -0.5 -3.0 - - 1 : 2.9 - - 12 20 5 1.4 TYP. MAX. 30 45 - - - 1.65 - 1.3 1.3 - 7.3 - - -3 730 20 15 x 1.0 1.0 20 -4.0 6.0 -0.7 +3.0 - - - 103 UNIT V V mA mA mA V V V A A A V V mA s V A V A V mA V V % K-1 K-1
V6 - 2.3 V6 - 2.0 - - -0.1 6.8 5.7 300 - 680 - - - - - - - - - 10-4 4 x 10-4 1:3
V10 - 2.2 -
leakage current frequency detector higher frequency V13 = 50 V output voltage buffer stage output current buffer stage synchronizing input voltage synchronizing input voltage tolerance of free running oscillator
oscillator temperature dependency Tmb = 20 to 100 C oscillator voltage dependency VP = 10 to 30 V
synchronizing ratio
1997 Mar 27
8
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
TEST AND APPLICATION INFORMATION
TDA4800
handbook, full pagewidth
TDA4800
BLANKING PULSE GENERATOR +2 V GUARD CIRCUIT VOLTAGE STABILIZER
SYNC CIRCUIT
OSCILLATOR
RAMP BUFFER GENERATOR STAGE
PREAMPLIFIER
POWER OUTPUT STAGE THERMAL AND SOAR PROTECTION
FLYBACK GENERATOR
FREQUENCY DETECTOR
1
2
3
4 47 k
5
6
7
8 100 F
9
10
11
12
13 frequency criterion 50 Hz: low 60 Hz: high
100 k 47 k 100 nF 330 k (frequency) 100 k 15 k linearity 1N4148 vertical deflection unit 6.5 15 k 4.7 k 100 120 6.5 mH 560 (0.5 W) 2200 F 0.82 (0.5 W) BAX18
100 nF
100 nF 100 nF 5.6 100 F 3.3 (4 W)
180 k (R)
10 nF (C)
10 k 47 nF 10 F
blank pulse duration: tbl = R x C x Ln2
562 k
or sync input blank output
amplitude 2.2 k
1.5 k
100 nF
Vamplitude
VP2 = 23 V
MHA589
Fig.4 Test and application circuit.
1997 Mar 27
9
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
TDA4800 in the test and application circuit (see Fig.4) SYMBOL VP2 IP V7 V7M I7 IY(p-p) tfb tbl Ptot fo supply voltage supply current DC output voltage peak output voltage output current vertical deflection current (peak-to-peak value) flyback time blanking pulse duration total power dissipation free running oscillator frequency without sync PARAMETER CONDITIONS 23 215 11.8 45 0.8 1.5 0.3 1.25 3.3 45
TDA4800
TYP. V
UNIT mA V V A A ms ms W Hz
1997 Mar 27
10
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
TDA4800
SOT141-6
non-concave x D Dh
Eh
view B: mounting base side
d
A2
B j E A
L3
L
Q c
1 Z e e1 bp wM
13 m e2 vM
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT141-6 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A 17.0 15.5 A2 4.6 4.2 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 3.4 e1 1.7 e2 5.08 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.25 x 0.03 Z (1) 2.00 1.45
ISSUE DATE 92-11-17 95-03-11
1997 Mar 27
11
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
MOUNTING INSTRUCTIONS FOR 13-LEAD DBS13P POWER PACKAGE The rise in temperature caused by power dissipation in the circuit is reduced by adding a heatsink with a sufficiently low thermal resistance: Rth(mb-h) + Rth(h-a) = Rth(mb-a) (e.g. the heatsink of Fig.5). It is possible to attach the package to the heatsink by screws (Fig.6) or by a compression spring (Fig.7). A layer of silicon grease between the heatsink and the mounting base optimizes thermal contact.
TDA4800
86
50
18.5 10.5 27 27 10
1.5
3.5
3.5
5 22.5 63.5 Dimensions in mm. M2.5 (2x)
MHA585
Fig.5 Heatsink made of black-leaded Aluminium.
page
,, ,, ,, ,, ,, ,, ,, ,, ,,
Fig.6
heatsink
handbook, halfpage
27 6
8.5 4.5 12
22 0.4 PC board 30
MHA587
MHA586
Dimensions in mm.
Package and heatsink attached by screws.
Fig.7
Compression spring for easily attaching the package to the heatsink of Fig.5.
1997 Mar 27
12
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4800
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Mar 27
13
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
NOTES
TDA4800
1997 Mar 27
14
Philips Semiconductors
Product specification
Vertical deflection circuit for monitor applications
NOTES
TDA4800
1997 Mar 27
15
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp16
Date of release: 1997 Mar 27
Document order number:
9397 750 01396

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